English to French Tech/Engineering Patents telecommunications,

The microcomputer 10 includes a CPU 11 for performing various tasks, a flash memory (FLASH) 13, a RAM 15 serving as a working
memory for the CPU 11, an interrupt controller 17, a user break controller (UBC) 18, and an interface (I/F) 19 for allowing the CPU 11 to communicate with extemal devices. The CPU 11, the flash memory 13, the RAM 15, the interrupt controller 17, the user break controller 18, and the interface 19 communicate with each other via buses 50 including data buses and address buses.

Referring to Fig. IB, the user break controller 18 is integrated with a break address register 18a and a break condition comparator 18b. For example, to the break address register 18a, at least one address is set.
When a function (an instruction) whose address has been set to the break address register 18a is carried out by the CPU 11, the break condition controller 18b works to receive the address via the address buses 50, and détermine that a predetermined break condition is met, thus inputting, to the CPU 11 via the interrupt controller 17, a break interrupt request.

a user break controller (18) integrated with a break address register (18a) and configured to generate the interrupt request every time one of the plurality of routines corresponding to an address set to the break address register (18a) is executed;